Wafer scale integration.

Wafer Scale Integration of Parallel Processors

A RAM-based Neural Network Architecture for Wafer Scale Integration

While the use of WSI technology to increase the integration density of RAM devices may not be cost effective (cf. Anamartic’s failed WSI RAMs [23]), low defect tolerance overheads, high testability, and low power consumption make memories ideal building blocks for WSI processor architectures. Indeed, this is reflected in the number of memory-based WSI devices manufactured to date [15,19,22,23,24].

Three Dimensional Integration and On-wafer Packaging for Heterogeneous Wafer-scale Circuit Architectures

Advanced Network Centric Warfare (NCW) systems are critical to the successful implementation of the Army’s Future Force. These systems require a new generation of circuits with deployable, agile, versatile, lethal, survivable and sustainable capabilities. Both manned and unmanned vehicles are required to established dominance in the battlefield via use of multi-band, agile, multifunctional mobi...

Wafer-Scale VLSI Testing

1 Introduction In the manufacturing of VLSI integrated circuits (ICs), it would be desirable that the ICs undergo an accurate test directly on the wafer, before they are cut and packaged. This would save the cost of bounding and packaging the faulty ICs, which may be a relatively large fraction. However, accurate testing on the wafer can hardly be supported by the consolidated technology of tes...

Wafer-level 3D integration technology

integration technology S. J. Koester A. M. Young R. R. Yu S. Purushothaman K.-N. Chen D. C. La Tulipe, Jr. N. Rana L. Shi M. R. Wordeman E. J. Sprogis An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as t...